With the scaling of integrated circuits, metal-oxide-semiconductor (MOS) devices are becoming increasingly smaller. The junction depths of the MOS devices are also reduced accordingly. This reduction causes technical difficulties during the formation processes. For example, small MOS devices demand high doping concentrations in source and drain regions in order to reduce sheet resistance in the source and drain regions. This results in the doping profiles to be more abrupt.
FIG. 1 schematically illustrates a cross-sectional view of an intermediate stage in the formation of a MOS device. Gate dielectric 4 and gate electrode 6 are formed on semiconductor substrate 2. Source/drain extension (SDE) regions 8 are formed in substrate 2 by vertically implanting an impurity. Halo/pocket regions 10 are also formed in substrate 2 by implanting an impurity having an opposite conductivity type than SDE regions 8. Preferably, halo/pocket regions 10 are tilt implanted so that they extend more into the channel region. Halo/pocket regions 10 also preferably extend deeper into substrate 2 than SDE regions 8. SDE regions 8 and halo/pocket regions 10 were typically formed using a same mask.
The formation methods shown in FIG. 1 suffer from drawbacks. With the increasing down-scaling of integrated circuits, SDE regions 8 and halo/pocket regions 10 became increasingly shallower. Accordingly, the doping concentrations of SDE regions 8 and halo/pocket regions 10 became more abrupt. This causes band-to-band tunneling leakages, which are the leakages between the source/drain regions (not shown) and substrate 2, to increase. Further, the band-to-band tunneling leakages may occur throughout the source/drain regions (from regions substantially under gate electrode 6 to regions away from gate electrode 6), further increasing the band-to-band tunneling leakage currents.
FIG. 2 schematically illustrates a profile of halo/pocket regions 10, wherein regions 12 represent where halo/pocket impurities are located. It is noted that the highest impurity concentration is in regions 121, which are under the surface of substrate 2. The impurity concentration gradually decreases from regions 121 to regions 122, and to regions 123. Since regions 12 overlap the source/drain regions, the net impurity concentration of source/drain regions will be offset by the implanted halo/pocket impurity. As a result, the source/drain resistance adversely increases.
Therefore, what is needed in the art is a new MOS device structure having reduced leakage currents and a reduced source/drain resistance, and manufacturing methods for forming the same.